1. Field of the Invention
This invention relates to a semiconductor memory device, and more particularly to an EPROM in which readout data is detected according to the potential difference between a memory cell output and a dummy cell output.
2. Description of the Related Art
A semiconductor memory device generally has an input terminal connected to receive a chip enable signal CE which is used to selectively set the semiconductor memory device into an active state or standby state. In connection with the control, chip enable signal CE is supplied from the input terminal to a buffer amplifier and is converted to a chip enable signal CEl having an amplitude suitable for a memory circuit. In general, the memory circuit is set into the standby or active mode when chip enable signal CEl is at "1" or "0" level, respectively. In the standby state, it is prevented that current unnecessarily flows in the memory device. Therefore, the power consumption in the standby state is lower than that in the active state.
FIG. 1 is a diagram schematically showing the memory circuit of the conventional EPROM. In this memory circuit, floating gate type memory cells are used. The readout operation is effected by a power source voltage supplied from power source terminal VCC when chip enable signal CEl is at "0" level. In the readout mode, a row decoder RD decodes a row address signal to selectively supply a readout voltage to one of word lines WLl is WLn, and a column decoder CD decodes a column address signal to selectively turn on one of MOS transistors Tll to Tlm. For example, when memory cell MCll is specified by row and column address signals, a readout voltage is supplied to memory cell MCll via word line WLl. At this time, the conduction state of memory cell MCll is determined according to the stored data. That is, the memory cell MCll is turned on or off when the stored data is "1" or "0", respectively. The stored data is read out by detecting the potential of bit line BL1 which is set according to the conduction state of memory cell MCll. The readout data is supplied to data line DL1 via MOS transistor Tll, and is also supplied to sensing circuit 2 via MOS transistor T8 and data line DL2. Sensing circuit 2 compares input potential VD corresponding to the readout data with reference potential VREF supplied from reference potential generating circuit RS, and generates output signal "0" or "1" according to the potential difference therebetween. Thus, sensing circuit 2 supplies an output signal to drive output circuit 1 which in turn supplies output data of the logic value corresponding to the readout data to the exterior. Reference potential VREF is set to a potential level between potentials of data line DL2 respectively set when data "1" and "0" are read out.
In the EPROM, as shown in FIG. 1, reference potential generating circuit RS is formed to have a construction equivalent to that of main body circuit MS. With this construction, the condition in which the potential of dummy data line DDL2 or reference potential VREF is set according to dummy data read out from one of dummy cells DMCl to DMCn can be set to correspond to that in which the potential of data line DL2 is set according to data read out from one of memory cells MCll to MCnm. However, it is necessary to constitute reference potential generating circuit RS so as to set reference potential VREF to a preset potential level, and therefore it cannot be formed to have exactly the same construction as main body circuit MS. For example, N-channel MOS transistor T0 is formed to correspond to N-channel MOS transistors T1 to Tlm, but the gate of N-channel MOS transistor TO is connected to power source terminal VCC which is set at 5 V, and therefore, unlike MOS transistors Tll to Tlm, MOS transistor T0 is kept set in the conductive state. Further, load transistor T1 for the dummy cell has a larger current supplying ability than that of load transistor T2 for the memory cell to set reference voltage VREF to a potential level between the potentials of data line DL2 respectively set when data "1" and "0" are read out.
The conventional construction described above may cause unwanted data to be read out after the memory circuit is activated. When chip enable signal CE1 is at "1" level, that is, when the memory circuit is set in the standby mode, data lines DL1 and DL2 and data lines DDL1 and DDL2 are set at 0 V. When chip enable signal CE1 falls from "1" level to "0" level, a charging current flows from power source terminal VCC into data lines DL2 and DL1 via load MOS transistors T2 and T7, and at the same time into data lines DDL2 and DDL1 via load MOS transistors T1 and T9. The potentials of data lines DL1, DL2, DDL1 and DDL2 rise from 0 V by the charging operation of load MOS transistors T2, T7, T1 and T9. At this time, row decoder RD, column decoder CD, sensing circuit 2 and output circuit 1 are also started to operate at the time of fall of chip enable signal CEl. As shown in FIGS. 2A and 2B, potential VD of data line DL2 rises at a higher rate in comparison with potential VREF on data line DDL2. This is because data lines DL1 and DL2 are electrically isolated from bit lines BLl to BLM while the parasitic capacitance associated with bit line DBL is charged together with the parasitic capacitances associated with data lines DDL1 and DDL2 via MOS transistor T0. Output signals COl to COm from column decoder are set at "0" level during the period in which chip enable signal CEl is set at "1" level. The decoding operation of column decoder CD is started when chip enable signals CE1 falls to "0" level. After the decoding operation has finished, one of output signals COl to COm is set at "1" level to turn on a corresponding one of MOS transistors Tll to Tlm. Therefore, the timing that one of bit lines BLl to BLm is electrically connected to data lines DL1 and DL2 via the corresponding MOS transistor is delayed according to the response time of column decoder CD. When potential VD becomes higher than potential VREF, sensing circuit 2 sets the potential of data line DS to "0" level, and an output potential of output circuit 1 is set to "0" level as data "0".
When gate voltage COl of MOS transistor Tll is raised by column decoder CD according to the decoding result, for example, MOS transistor Tll is turned on to electrically connect bit line BLl to data line DL1. At this time, part of charges stored in the parasitic capacitance of data lines DL1 and DL2 is supplied to the parasitic capacitance of bit line BLl, and potential VD of data line DL2 is lowered and then is raised again. When potential VD of data line DL2 becomes lower than potential VREF of data line DDL2 as shown in FIGS. 2A and 2B, sensing circuit 2 sets the potential of data line DS to "1" level, and the output potential of output circuit 2 is changed to "1" level as data "1".
The decoding operation of row decoder RD is completed with a delay time with respect to the decoding operation of column decoder CD. For example, if row decoder RD raises the potential of word line WLl based on the decoding result, the potential of bit line BLl is set according to the conduction state of memory cell MCll and at the same time the potential of bit line DBL is set according to the conduction state of dummy cell DMC. At this time, potential VREF of data line DDL2 is lowered and set at a predetermined level.
For example, in a case where data "0" is stored in memory cell MCll, potential VD of data line DL2 is further raised and set to a potential level higher than potential VREF as shown in FIG. 2A When potential VD of data line DL2 becomes higher than potential VREF of data line DDL2, sensing circuit 2 sets the potential of data line DS to "0" level, and the output potential of output circuit 1 is changed to "0" level as data "0". Reference potential VREF rises at a higher rate than potential VD after MOS transistor Tll is turned on. This is because load transistor T1 has a larger current supplying ability than load transistor T2 as described above. In this case, the time required for potential VD to be set at a higher level than potential VREF becomes longer.
In contrast, in a case where data "1" is stored in memory cell MCll, rise in potential VD of data line DL2 is stopped and potential VD is set at a potential level lower than potential VREF as shown in FIG. 2B. When potential VD of data line DL2 becomes lower than potential VREF of data line DDL2, sensing circuit 2 sets the potential of data line DS to "0" level and the output potential of output circuit 1 is kept at "1" level as data "1".
In a case where data read out from the memory cell is "0", output data Dout is first set to "1" and thenchanged to "0". In this case, time required for determining output data Dout becomes longer by the time for discharging the charge stored in output terminal PD. On the other hand, when output terminal PD is alternately charged and discharged in a short period of time, power source noise can be produced.
In the prior art method, in order to prevent unwanted data from being output, time for starting to operate sensing circuit 2 and the load circuits in reference potential generating circuit RS and main circuit MS after the rise of chip enable signal CEl is further delayed. In this case, the above circuits are operated after data has been read out from a selected memory cell, thus preventing unwanted data from being supplied from output circuit 1.
However, in this method, since the operation of charging data lines DL1 and DL2 and dummy data lines DDL1 and DDL2 is started after the load circuits in reference potential generating circuit RS and main circuit MOS transistor have been operated, it will be impossible to sufficiently shorten the time for the data readout operation.
Further, in order to solve this problem, a method of holding the bit and dummy bit lines at a preset potential in the standby mode is provided. With this method, even if the load circuits of reference potential generating circuit RS and main circuit MS are operated after data has been read out from a selected memory cell, data can be exactly read out at a high speed because the operation of charging the bit line has already been completed. However, if the preset potential is kept applied to the bit line, the memory cell connected to the bit line may be influenced, and if the memory cell is of a floating gate type, data may be destroyed, as described below:
In the floating gate type EPROM cell, the state in which electrons are injected into the floating gate to raise the threshold voltage indicates data "0" and the state in which electrons are not injected to hold the originally set threshold voltage indicates data "1". Therefore, if the preset voltage is kept applied to the data line as described before, a potential is applied to the drain of the EPROM cell transistor so that the electrons in the floating gate may be moved into the drain, thus lowering the threshold voltage. As a result, the content of the memory cell may be sometimes changed from "0" to "1".